The present invention relates to semiconductor integrated circuits and more particularly to synchronizing read data from a memory device with a memory controller""s clock signal.
Certain types of memory devices generate a clock strobe signal having edges that are aligned with changes in the read data. A double data rate (DDR) dynamic random access memory (DRAM) transfers data on each rising and falling edge of the clock strobe signal. A DDR DRAM therefore transfers two data words per clock cycle.
A memory controller is often used to coordinate the transfer of data to and from a memory device, such as a DDR DRAM. The memory controller provides a local clock signal to the memory device for synchronizing read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the memory controller. The memory controller uses the clock strobe signal for determining when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the clock strobe signal so as to latch the read data in the middle of the valid data window.
Due to varying propagation delays from the memory controller""s local clock signal and the clock strobe signal that is received from the memory device, the phase relationship between the captured read data and the local clock signal can change from one device to the next and can change over time. These changes in phase alignment can be caused by input/output (I/O) pad delay variations, power supply fluctuations, process variations, temperature variations and variations in the clock input to data clock strobe output characteristics of the memory device. In certain cases these changes can be large enough to cause the captured read data to cross a metastable region with respect to the memory controller""s clock.
Due to these and other factors, accurate synchronization of the captured read data to the memory controller""s clock requires the phase relationship between the data output clock strobe signal and the memory controller""s clock to be known. Currently, there is no known method or system for measuring and correcting for changes in this phase relationship. Improved memory controller circuits are therefore desired that are capable of measuring the phase relationship between a memory controller""s clock and captured read data from a memory device, where the data is aligned with respect to a delayed clock strobe signal that originates from the memory device.
One embodiment of the present invention is directed to an apparatus for capturing data read from a memory device that is aligned with respect to a clock strobe signal originating from the memory device, wherein the strobe signal has constraints with respect to a local clock signal supplied to the memory device. The apparatus includes a circuit for capturing the data read from the memory device relative to the clock strobe signal to produce captured read data, a circuit for latching the captured read data relative to a sample clock signal, and a circuit for measuring a phase difference between the sample clock signal and the clock strobe signal and adjusting a phase of the sample clock signal as a function of the phase difference.
Another embodiment of the present invention is directed to a method of capturing data read from a memory device that is aligned with respect to a clock strobe signal originating from the memory device, wherein the strobe signal has constraints with respect to a local clock signal supplied to the memory device. The method includes capturing the data read from the memory device relative to the clock strobe signal to produce captured read data, latching the captured read data relative to a sample clock signal, measuring a phase difference between the sample clock signal and the clock strobe signal, and adjusting a phase of the sample clock signal as a function of the phase difference.